In the field of semiconductor fabrication, with very-large-scale integration (VLSI) becoming the development trend, the feature size of integrated circuits steadily decreases. To accommodate the decrease of the feature size, the channel length in metal-oxide-semiconductor field-effect-transistors (MOSFET) also continuously decreases. However, as the channel length of devices becomes shorter, the distance between the source region and the drain region in the devices may also be reduced. Therefore, the gate electrode in traditional planar MOSFETs may not have sufficient ability to control the channel. It becomes more difficult for the gate voltage to pinch off the channel, and thus the subthreshold leakage phenomena, i.e. the short-channel effects may easily take place.
In order to better adapt to the decrease of the feature size, semiconductor fabrication technology gradually changes from planar MOSFETs to more efficient three-dimensional (3D) transistors, such as fin field-effect-transistors (Fin-FETs). In a Fin-FET, gate electrode is able to control an ultra-thin structure (e.g., a fin structure) from the two side surfaces of the ultra-thin structure. Therefore, Fin-FETs demonstrate much better gate-to-channel controllability than planar MOSFETs. As such, Fin-FETs may be able to significantly suppress the short-channel effects. In addition, compared to other devices, Fin-FETs may also demonstrate better compatibility with the existing fabrication technology for integrated circuits.
Fin-FETs may be classified mainly into two categories based on their functions, namely, core devices and peripheral devices (e.g. input/output (I/O) devices). In addition, according to the electrical types of the devices, the core devices may be further categorized into two types: core N-type metal-oxide-semiconductor (NMOS) devices and core P-type metal-oxide-semiconductor (PMOS) devices; and the peripheral devices may be further categorized into two types: peripheral NMOS devices and peripheral PMOS devices.
Generally, the operation power voltage of the peripheral devices is significantly larger than the operation power voltage of the core devices. Therefore, the thickness of the gate dielectric layers in peripheral devices is usually larger than the thickness of the gate dielectric layers in core devices. In order to prevent electrical breakdown and other issues, for a device with a high operation power voltage, the thickness of the gate dielectric layer in the device may need to be increased. The thickness of the dielectric layers in peripheral devices may also need to be increased.
However, the electrical performance of existing semiconductor structures may still need to be improved. The disclosed semiconductor structures and fabrication methods thereof are directed to solve one or more problems set forth above and other problems in the art.